ALMA project

ALgorithm parallelization for Multicore Architectures.

Simplifying programming for multi-cores

Why must a programmer care for the hardware architecture when programming embedded applications on a multiprocessor Systems-on-Chip?
The ALMA project intends to change that 'MUST' into a 'MAY'. We work to develop a programming tool chain that hides the complexity of applications and architectures from the programmer, and creates optimized code at the same time.

Glossary

ALMA uses many different terms that might not be so familiar, as developing tools for many-cores systems is a relatively new research area. Please find below our glossary to help you understand:

AADLArchitecture Analysis and Design Language
ADLArchitecture Description Language
AMBAAdvanced Microcontroller Bus Architecture
AMPAsymmetric MultiProcessing
APIApplication Programming Interface
ASGAbstract Syntax Graph
ASTAbstract Syntax Tree
AVXAdvanced Vector Extensions
BUGBottom-Up-Greedy
CDFGControl and Data Flow Graph
CFGControl Flow Graph
CILCommon Intermediate Language
CPUCentral Processing Unit
CRISPCutting edge Reconfigurable ICs for Stream Processing
DSLDomain-Specific Language
DTSE Data Transfer and Storage Methodology
GCCGNU Compiler Collection
GPPGeneral Purpose Processor
GSPGeneral Streaming Processor
DSPDigital Signal Processor
ELFExecutable and Linking Format
EULAEnd User Licence Agreement
GPUGraphics Processing Unit
GPGPUGeneral Purpose Graphics Processing Unit
HDLHardware Description Language
HIRHigh Level Intermediate Representation
HLAHigh Level Synthesis
HPCHigh Performance Computing
IMSIntegrated Modulo Scheduling
ILPInstruction Level Pipelining
IRIntermediate Representation
ISAInstruction set architecture
JITJust In Time
KAHRISMAKArlsruhe's Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Processor
LIRLow Level Intermediate Representation
LISALanguage for Instruction Set Architecture
LISPIs a family of computer programming languages
LLVMLow-Level Virtual Machine
LTILinear Time-Invariant
MCAMulticore Association
MMXMulti Media Extension
MPSoCMultiprocessor System on Chip
MPPBMassively Parallel Processor Breadboarding
NLPNested Loop Programs
NPNon-Polynomial
NoCNetwork on Chip
NUMANon-Uniform Memory Access
OpenCLOpen Computing Language
PCCAPartial Component Cluster Assignment
PISPragmatic Integrated Scheduling
PIPParametric Integer Programming
PEMBICPEloponnese ALMA Scilab/MATLAB BITcode
PTXParallel Thread eXecution
RHOPRegion-based Hierarchical Operation Partitioning
RTLRegister Transfer Level
RFDReconfigurable Fabric Device
SCoPStatic Control Part
SIMDSingle Instruction Multiple Data
SMPSymmetric MultiProcessing
SoCSystem-on-Chip
SRAStrategic Research Agenda
SSAStatic Single Assignment
SUIFStanford University Intermediate Format
SWPSub-Word Parallelism
UASUnified Assign and Schedule
UMAUniform Memory Access
VHDLVery high speed integrated circuits Hardware Description Language
VLIWVery Long Instruction Word
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